1. Technical Field
The present invention relates to circuit design and more particularly to systems and methods for scaling integrated circuits to accommodate different technologies and components.
2. Description of the Related Art
Many applications are improved through the use of integrated circuits. Integrated circuits provide a compact, reliable and cost effective way of implementing circuitry in many different systems. With the advance of technology, integrated circuits are often scaled to permit the use of an old circuit design with the new technology. There are many problems that result from scaling circuitry.
One particularly difficult instance includes the scaling of a static random access memory (SRAM). Referring to FIG. 1, an illustrative circuit 10 includes an SRAM cell 12, a word decoder 14 and a bit select circuit 16, In SRAM circuit layouts, size or scaling of the circuit in the x-direction is different then the scaling in the y-direction. The difference in x and y scale factors is to achieve gains in performance and stability of the circuits.
The SRAM cell 12 has a greater impact on the x-direction pitch and therefore has a large influence on the x-direction pitch for the bit select circuit 16 and back-end wiring. The word decoder 14 is substantially influenced by the y-direction pitch. The word decoder 14 (and peripheral logic) scale with respect to the technology permitted by a polysilicon grid (e.g., a minimum feature size of the semiconductor processing technology). The poly grid refers to the polysilicon typically formed in lines or grids being spaced in accordance with a minimum feature size for gates which in effect determines the transistor size. The poly grid usually determines the correct spacings for source and drain implant regions and therefore the spacings of transistors.
The x-pitch of the bit select circuitry 16 and back end wiring scale with respect to migration rules. Migration rules are ground rules that govern aspects of the chip layout and permit different or optimal positioning of circuits or components. FIG. 1 depicts conventional circuitry including bitlines (blc and blt), word line W1, bit select circuits (Bit sel0 through Bit seln), a dominion read circuit 17, output latches 19 and a word line driver 15. The bit select circuit 16 includes inputs from a bit driver, read/write driver, data driver and a reset driver.
Since the x and y directions are influenced by different factors, the SRAM cell 12 becomes extremely difficult to scale. The SRAM cell 12 does not easily scale in accordance with both the x and y scalings especially between different technology types (e.g., one generation of a chip design to the next). Current, manipulation tools prove inadequate at addressing the problems of scalability for circuits like the SRAM cell 12, One such tool includes a migration assistant shapes handler (MASH).
Referring to FIG. 2, a basic process flow for a MASH system is illustratively depicted. A design 50 with complicated shapes is input. The shapes may represent portions of a circuit such as gates, contacts, metal lines, etc. In block 52, a sophisticated shapes preprocessor processes the locations, shapes, sizes, etc. of the shapes in the design to permit a workable layout 51. This information is input to an optimization engine 52 along with ground rules and controls from a module 54. Engine 52 checks the shape layout against the ground rules and other criteria to ensure that no rules or constraints are violated. Then, the layout optimization engine 52 (e.g., EMMA), is employed to optimize the sizes and locations of the shapes in accordance with the ground rules and controls. During the optimization, ground rule errors are corrected or variances granted to provide a desired/optimized layout 56.
The MASH tool may employ parameterized cells (P cells). P-cells at device and gate levels of a design do not permit the ability for wire migration especially at upper levels of a design. P-cells may permit the generation of custom or semi-custom layouts at the device or gate level. By specifying the width and length of a device, and/or other device options, the P-cells can automatically be placed and routed based on the connectivity of the devices in the layout. The MASH system does not maintain the integrity of the P-cells and does not scale custom SRAM arrays. In addition, for back end wiring, especially at higher levels in the design, scaling is difficult.